I am currently a postdoctoral researcher at the KAIST Mixed Signal Integrated Circuits Laboratory (MSICL) under the 2025 KAIST Jang Young Sil Fellow Program (Excellence Track).

I received my Ph.D. in electrical engineering from KAIST in 2025 under the supervision of Professor Seung-Tak Ryu. My research interests focus on mixed-signal integrated circuit design with an emphasis on data converters. I worked on high-resolution and low-power analog-to-digital converters (ADCs), continuous-time (CT) and hybrid ADCs (e.g., SAR-assisted ADCs), and delta-sigma modulators (DSMs).

During my M.S.-Ph.D. studies, I focused on developing a high-resolution, low-power, digital-intensive ADC architecture. Specifically, I worked on a digital-intensive SAR-assisted CT DSM architecture, which offers significant advantages over discrete-time (DT) ADCs, such as inherent anti-aliasing and ease of driving.

My contributions have been widely recognized at numerous top-tier IEEE conferences and journals, including the IEEE Symposium on VLSI Technology and Circuits (VLSI Circuits), IEEE Custom Integrated Circuits Conference (CICC), IEEE Journal of Solid-State Circuits (JSSC), etc. I have also received numerous paper invitations, presentation opportunities, and several awards.